1. Field
Example embodiments relate to a method of programming a nonvolatile memory device, and for example, to a method of programming a nonvolatile memory device which may more efficiently reduce a threshold voltage distribution in a program state.
2. Description of Related Art
Nonvolatile memories are storage devices capable of storing data even if a supply of power is discontinued. Floating gate type flash memories, which are operated by storing electric charges in a floating gate formed of polysilicon, have been commercialized as an example of larger capacity nonvolatile memories. A memory cell of a flash memory is classified into a single level cell (SLC) type in which two recording states of “1” and “0” are recorded in a single cell and a multi-level cell (MLC) type in which four or more recording states, for example, “11”, “10”, “01”, and “00”, are recorded in a single cell.
Multi-level cell technology is used in making a larger capacity NAND or NOR type flash memory. In an operation of a MLC, each recording state may be separately recognized only if the distribution of threshold voltages Vth of cells corresponding to a respective recording state is relatively smaller.
An incremental step pulse programming (ISPP) scheme for repeatedly applying a program voltage Vpgm while constantly increasing the program voltage Vpgm may be used to reduce a threshold voltage distribution between memory cells in a flash memory. According to the ISPP scheme, a step of applying a program voltage pulse while increasing the amount of an input program voltage pulse by ΔVpgm and checking a threshold voltage of a memory cell by applying a verifying voltage pulse is repeated so that the threshold voltage of the memory cell reaches a desired, or alternatively, a predetermined value. Because a plurality of memory cells forming the flash memory have an initial threshold voltage distribution, the ISPP scheme is introduced to allow all memory cells to reach a desired, or alternatively, a predetermined threshold voltage considering the threshold voltage distribution for each memory cell.
However, as a size of cells decreases in flash memories using a floating gate, coupling between cells, e.g., coupling between the floating gates, increases so that controlling the distribution of the threshold voltage is more difficult. Recently, to reduce the coupling between cells in an attempt to address the above problem of controlling the distribution of the threshold voltage, a charge trap flash (CTF) memory using, instead of the floating gate, an insulation layer including a charge trap site, for example, a charge trap layer, (e.g., silicon nitride Si3N4), which may trap electric charges, has been developed.
During programming of the CTF memory, injected electrons are trapped in the charge trap layer and localized therein. The injected electrons are thermalized in a deep trap and spatially spread throughout a nitride film. Accordingly, because the threshold voltage of a device changes as the electrons are thermalized and spatially spread, a certain time may be required until the threshold voltage Vth is fixed due to the localized electron thermalization.
Therefore, in the CTF memory, the threshold voltage Vth characteristically changes according to the time after programming due to the movement of the charges trapped in the charge trap layer after programming. The time-dependent threshold voltage change makes controlling the distribution of a threshold voltage during programming in the ISPP scheme more difficult.
If the threshold voltage Vth changes according to the time, an error may occur in the verification of a program state after a desired, or alternatively, a predetermined time passes after the programming. Due to the verification error, the distribution of a threshold voltage of a program state obtained by the ISPP type program increases.
For example, if the threshold voltage changes according to the time, even if the threshold voltage may reach a target value as time passes, a verification error that a memory cell has failed to reach the threshold voltage may occur as a result of verification. If the target threshold voltage is determined to have not been reached, a program voltage increased by ΔVpgm is applied for programming, and therefore, an over-program may occur in which the threshold voltage excessively increases. Accordingly, the distribution of the threshold voltage of the program state may increase.